The present invention relates to a data processing system having a plurality of processors and, more particularly, to a technology which allows an easy access to a shared resource such as a shared memory used in common by the plurality of processors, and is useful in exclusively accessing the respective local memories of the processors.
Non-Patent Document 1 shown below discloses a multiprocessor architecture in which a plurality of processors having respective local memories are coupled to a global bus via bus bridges termed transactors. A global memory is coupled to the global bus. A central arbiter is coupled to the global bus and to the plurality of bus bridges. The central arbiter monitors a transaction on the global bus. When one of the multiple processors terminates a write transaction, the central arbiter requests the bus bridge of the next processor in the sequence of processes to generate a read transaction. After acquiring the request for the read transaction, the bus bridge interrupts the corresponding processor, acquires a local memory address, and stores data from the global memory in the local memory.
On the other hand, a spin lock method has been conventionally known as a method for exclusively accessing the shared memory of a multiprocessor. In the spin lock method, one of multiple processors determines from a lock variable whether or not the shared memory is usable before accessing the shared memory. When the shared memory is usable, the one of the multiple processors rewrites the lock variable from a usable state (e.g., a “0” level) to an in-use state (e.g., a “1” level) and exclusively accesses the shared memory. When the access to the shared memory is completed, the one of the multiple processors rewires the lock variable from the in-use state (e.g., the “1” level) to the usable state (e.g., the “0” level). The spin lock method is disclosed in, e.g., Non-Patent Document 2 shown below.
In a round robin system, unlike in the spin lock method, an execution time on a bus is divided into a plurality of even time slots and successively allocated to a plurality of bus masters by time-division multiplex scheduling. The round robin method is disclosed in, e.g., Non-Patent Document 3 shown below.
[Non-Patent Document 1] Jin Lee et al., “Orthogonalized Communication Architecture for MP-SOC with Global Bus”, 2005 Proceedings Fifth International Workshop on System-on-Chip for Real-Time-Applications, 20-24 Jul. 2005 PP. 541-545
[Non-Patent Document 2] THOMAS E. ANDERSON, “The performance of Spin Lock Alternatives for Shared-Memory Multiprocessors”, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 1, NO. 1, JANUARY 1990, PP. 6-16
[Non-Patent Document 3] Chang Hee Pyoun et al., “THE EFFICIENT BUS ARBITRATION SCHEME IN SOC ENVIRONMENT”, 2003 Proceedings The 3rd International Workshop on System-on-Chip for Real-Time-Applications, 30 Jun.-2 Jul. 2003 PP. 311-315